The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, three dimensional integrated circuits have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a three dimensional integrated circuit, active circuits such as logic, memory, processor circuits and/or the like are fabricated on different wafers and each wafer die is stacked on top of a packaging component using pick-and-place techniques. Much higher density can be achieved by employing three dimensional integrated circuits. In sum, three dimensional integrated circuits can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.
In order to connect electrical circuits in the stacked semiconductor dies, through silicon vias are employed to provide a vertical connection channel through the body of stacked dies. Through silicon vias can be formed by using suitable techniques. For example, in order to form a through silicon via, an opening may be formed on an active side of the semiconductor substrate, wherein the opening extends deeper into the semiconductor substrate than the active devices of the semiconductor substrate. These openings may then be filled with a conductive material such as copper, aluminum, tungsten, silver, gold and/or the like. After the openings have been filled, the backside of the semiconductor substrate may be thinned through a thinning process such as a chemical mechanical polishing process or an etching process. The thinning process is applied to the backside of the substrate until the conductive material of the through silicon via is exposed.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.